1. Field of the Invention
This invention concerns an output circuit for outputting a high voltage output signal in response to a low voltage input signal.
2. Description of the Prior Art
Generally, a high voltage driving integrated circuit (IC) is used to drive a light emitting display, such as an electro luminescence (EL) display or a plasma display panel (PDP), since such display requires a high driving voltage.
In the driving circuit, a reduction of the switching time and the power consumption is required in addition to the requirement of the high voltage. Thus, a CMOS circuit is utilized to receive the input signal, and the output signal from the CMOS circuit is level shifted to a high voltage level by a push-pull type output stage. Usually, a DMOS (Double diffused MOS) transistor is used in the output stage.
FIG. 1 shows a circuit diagram of a conventional output circuit. In the circuit, a CMOS inverter circuit 3 including a P-channel type MOS transistor 1 and an N-channel type MOS transistor 2, is connected between the low power source voltage VDD and the ground VSS. The gate electrodes of the MOS transistors 1 and 2 are connected to the input terminal In.
The gate electrode of an N-channel type MOS transistor 5 is connected to the drain electrodes of the MOS transistors 1 and 2. The source electrode of the MOS transistor 5 is connected to the ground VSS.
The emitter electrode and a collector electrode of a multi-collector bipolar transistor 4 is connected to the drain electrode of the MOS transistor 5. The emitter electrode of the bipolar transistor 4 is supplied with a high power source voltage VCC.
The gate electrode of a pull-up MOS transistor 7 is connected to the remaining collector electrode of the bipolar transistor 4. The drain electrode of the MOS transistor 7 is supplied with the high power source voltage VCC. The source electrode of the MOS transistor 7 is connected to the output terminal Out.
The cathode and the anode of a Zener diode 8 are connected to the gate and the source electrode of the pull-up MOS transistor 7, respectively.
The source electrode of a pull-down MOS transistor 6 is connected to the ground VSS, and the drain electrode thereof is connected to the gate electrode of the pull-up MOS transistor 7.
The operation of the circuit is as follows. When the input signal IN is low level, the MOS transistor 1 in the CMOS inverter circuit 3 changes to the ON state, and the MOS transistor 2 changes to the OFF state. Thus, the MOS transistor 5 and the bipolar transistor 4 change to the ON state. Therefore, a predetermined voltage drop is developed at the Zener diode 8, and the pull-up MOS transistor 7 changes to the ON state. Thus, the parasitic capacitance and the load capacitance (not shown) at the output terminal Out are charged by the current of the MOS transistor 7, and the output signal level is raised substantially to the high power source voltage level VCC.
When the input signal IN changes to the high level, the MOS transistor 2 in the CMOS inverter circuit 3 changes to the ON state, and the MOS transistor 1 changes to the OFF state. Thus, the transistor 5 changes to the OFF state.
On the other hand, the pull-down transistor 6 changes to the ON state, since the input signal of the high level is supplied thereto. As the result, the parasitic capacitance and the load capacitance at the output terminal Out are discharged through the pull-down transistor 6, and the output signal level is lowered substantially to the ground level VSS.
In this circuit, it is necessary to continue the current supply by the bipolar transistor 4 for maintaining the MOS transistor 7 at the ON state to raise the output signal level to high level. Furthermore, a predetermined current continually flows through the bipolar transistor 4 and the MOS transistor 5 when the output signal level is high level, even if the output signal level becomes high level and the pull-up transistor 7 changes to the OFF state.
For example, the power consumption P becomes as follows assuming the current which flows through the MOS transistor 5 is 150 .mu.A and the high power source voltage VCC is 200 volts. EQU P=200.times.150.times.10.sup.-5 =30 mW (1)
Thus, the power consumption P becomes about 1 W when the display is 32 bits, since 32 output circuits shown in FIG. 1 are required. The more the output bits of the display, the more the power consumption.